华为于10月13日在上海举办2026麒麟媒体沟通会，首次公开麒麟9050 Pro芯片的详细架构图1。该芯片搭载新一代灵犀CPU、新一代马良GPU、新一代达芬奇架构NPU、新一代麒麟AI ISP等核心部件，还集成了灵犀微核、FFTS函数流任务调度器和安全处理器1。华为半导体业务无线终端芯片产品管理部部长徐松余表示，这是"首款逻辑折叠韬芯片——麒麟9050系列在中国半导体产业界的支持下成功量产"1。
尽管实现了量产，华为在发布会上坦言仍面临多项技术挑战1。这些挑战包括工具链和方法论、工艺差异补偿、跨层互联开销优化、能耗控制以及基准测试方法等1。为此，华为呼吁产业界和学术界开放合作，共同推动半导体技术的进一步发展1。
Huawei held a Kirin media communication event on October 13, 2024, in Shanghai, where it publicly disclosed the detailed architecture of its Kirin 9050 Pro chip for the first time 1. The company described the processor as its first logically-folded chip and confirmed that it has achieved mass production with support from China's semiconductor industry 1.
The Kirin 9050 Pro incorporates multiple core components, including a new-generation Lingxi CPU, Maliang GPU, Davinci architecture NPU, next-generation Kirin AI ISP, Lingxi micro-core, FFTS function flow task scheduler, and security processor 1. According to Xu Songyu, head of Huawei's wireless terminal chip product management department, the Kirin 9050 series represents a significant achievement enabled by collaborative efforts across the Chinese semiconductor sector 1.
Despite the successful launch, Huawei identified several substantial challenges requiring ongoing attention, including toolchain and methodology development, process variance compensation, cross-layer interconnect overhead optimization, power consumption control, and benchmark testing methodologies 1. The company has called upon both industry players and academic institutions to pursue open cooperation in addressing these technical obstacles and advancing future development 1.
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