研究团队提出面向高效张量计算的线程-寄存器解耦GPU执行模型FIBER

2026年8月20日，FIBER架构研究团队提出了一种用于高效张量计算的线程-寄存器解耦GPU执行模型 1。该研究提出的FIBER架构扩展了GPU的SIMT执行模型，将执行实例（fiber）与私有寄存器所有权解耦 1。在这种设计下，执行实例仅携带最小控制状态，并通过共享视图访问流式多处理器（SM）寄存器，从而实现动态并行度缩放和细粒度寄存器级数据流调度 1。

该架构扩展了指令集、微架构和编译器 1。在典型混合精度大语言模型（LLM）服务场景下，该架构在Ampere上实现了2.25倍的端到端加速（原始FP16计算为1.15倍），在Hopper上实现了1.8倍加速，在Blackwell上实现了2.09倍端到端加速 1。此外，其内核级增益最高达2.49倍 1。

A research team has proposed the FIBER architecture, a thread-register decoupled GPU execution model for efficient tensor computation, in a paper submitted on August 20, 2026 1. This architecture extends the GPU Single Instruction, Multiple Threads (SIMT) execution model by decoupling execution instances, referred to as fibers, from private register ownership 1. Each fiber carries only minimal control state and accesses streaming multiprocessor (SM) registers via a shared view 1. This decoupling enables dynamic parallelism scaling and fine-grained, register-level dataflow scheduling 1.

The FIBER architecture extends the instruction set, microarchitecture, and compiler to implement this execution model 1. In typical mixed-precision large language model (LLM) serving scenarios, the architecture achieves end-to-end speedups of 2.25x on Ampere, 1.8x on Hopper, and 2.09x on Blackwell 1. For original FP16 computation on Ampere, the speedup is 1.15x 1. At the kernel level, the FIBER model achieves performance gains of up to 2.49x 1.