SK海力士正在美国招聘人才，研发3D堆叠内存技术以解决端侧AI大模型运行中的性能制约1。这一技术方案通过将内存裸片直接压在处理器上，并在两块芯片间增加大量垂直数据通道，可望显著提升内存读写速度和处理器与内存的数据交互效率1。根据AMD官方数据，这种连接方式的密度可达传统平面封装的200倍以上1。相比之下，现有的HBM4内存带宽达2.8-3.3TB/s，而d-Matrix验证中的3DIMC单堆叠方案可达20TB/s1。
行业内已有类似尝试。英特尔在酷睿Ultra 200V系列中曾尝试将LPDDR5X内存直接集成到处理器封装内，最高可降低功耗40%1。然而该方案因内存容量固定（仅16GB和32GB两档）、成本高昂而遭到厂商不满，英特尔随后在酷睿300系列放弃了此方案1。与此同时，AMD的X3D处理器存在异常高温问题，涉及锐龙5000X3D到锐龙9000X3D系列1。业界预期芯片堆叠将成为未来趋势，但短期内仅限于旗舰机型应用1。
SK Hynix is recruiting talent in the United States to develop 3D stacked memory technology designed to address performance bottlenecks in on-device AI processing 1. The technology works by placing memory dies directly on top of processors and creating numerous vertical data channels between the two chips 1. According to AMD's official data, this connection approach can achieve a density over 200 times higher than traditional planar packaging 1.
The advancement promises significant improvements in memory read/write speeds and processor data interaction efficiency 1. For context, HBM4 memory achieves bandwidth of 2.8-3.3TB/s, while d-Matrix's verified 3DIMC single stacked solution reaches 20TB/s 1. Intel attempted a similar approach with its Core Ultra 200V series by integrating LPDDR5X memory into the processor package, reducing power consumption by up to 40 percent at its highest 1. However, the 200V series faced market resistance due to fixed memory capacity—only 16GB and 32GB options—and high costs, leading Intel to abandon this approach in the subsequent Core Ultra 300 series 1. Additionally, AMD's X3D processors have encountered unusual overheating issues across its lineup from the Ryzen 5000X3D to the Ryzen 9000X3D series 1.
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