一项技术研究详细揭示了Apple Neural Engine（ANE）在M1芯片中的内部架构设计。1研究通过反向工程方法，分析了ANE的计算核心、调度器、内存层次和DMA引擎等关键组件。1
M1芯片中的ANE配备16个计算核心，每个核心拥有128条FP16（或256条INT8）乘法累加通道，共计2048条并行MAC通道。1整体性能达到11 TOP/s，系统DRAM带宽为68 GB/s。1ANE采用固定功能数据流引擎设计，通过任务描述符进行配置，而非使用通用GPU指令集。1
在内存架构方面，ANE包含1 MiB的内核存储、16个L1暂存区和2 MiB的共享L2 SRAM。1数据传输层面，KernelDMA的读带宽为37.99 GB/s，TileDMA的读带宽为59.08 GB/s，而GPU读带宽可达77.70 GB/s。1研究指出，kernel和tile DMA请求按顺序而非并行执行，这一设计限制了DRAM的整体吞吐量。1
ANE架构原本为CNN工作负载优化，但在M5芯片中已被整合到GPU核心中，标志着独立NPU设计时代的终结。1
A detailed technical analysis has uncovered the internal architecture of Apple's Neural Engine (ANE) through reverse engineering of the M1 chip 1. The research reveals that the ANE features 16 compute cores, each equipped with 128 FP16 (or 256 INT8) multiply-accumulate channels, delivering a combined 2,048 parallel MAC lanes and achieving 11 TOP/s of performance 1.
The ANE operates as a fixed-function dataflow engine rather than a general-purpose GPU, configured through task descriptors instead of traditional instruction sets 1. The system incorporates a hierarchical memory structure comprising 1 MiB of kernel memory (KMem), 16 L1 scratchpads, and 2 MiB of shared L2 SRAM 1. Data movement through the architecture reveals distinct bandwidth characteristics: the Kernel DMA achieves read throughput of 37.99 GB/s, Tile DMA reaches 59.08 GB/s, and GPU memory access delivers 77.70 GB/s, with system DRAM providing 68 GB/s overall bandwidth 1. A key architectural constraint stems from sequential rather than parallel execution of kernel and tile DMA requests, which restricts DRAM throughput utilization 1.
The analysis indicates a significant shift in Apple's processor design philosophy, as the M5 chip integrates ANE cores directly into GPU cores, effectively marking the end of the independent NPU era 1.
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