IBM发布支持双指令集的新一代z18芯片

IBM在Hot Chips 2026大会上推出了支持z/Architecture和ARM双指令集的新一代z18芯片1。IBM工程师Christian Zoellin和Christian Jacobi详细介绍了该芯片的架构设计方案。

该芯片采用共享解码管道的设计，其中大部分解码细节实现共用，但部分解码器独立实现以适应两种指令集的差异1。在载入-存储单元中，芯片集成了硬件字节序转换功能，能够自动处理z/Architecture采用的大端字节序与ARM采用的小端字节序之间的转换1。值得注意的是，所有载入和存储指令被强制设置为强有序内存模型（TSO），而非ARM标准的弱有序模型1。

为支持新的数据处理需求，芯片新增了BF16和FP16浮点格式支持，所需的额外晶体管相对较少1。转换后备缓冲器、缓存和物理寄存器文件等大型结构则完全共享复用1。搭载在该芯片上的Spyre模块集成了HBM内存，单芯片内存带宽可达4TB/秒1。

IBM推出双ISA架构的目的是充分利用ARM生态系统的软件资源，支持从小型欺诈检测模型到大型语言模型和AI运维代理工作流等大规模工作负载的整合1。IBM特意不考虑添加POWER指令集，以避免与其Power Systems产品线产生竞争1。

IBM has introduced its next-generation z18 chip, designed to support both z/Architecture and ARM instruction sets, marking a significant shift in the company's processor strategy.1 Engineers Christian Zoellin and Christian Jacobi presented the architecture's technical details at the Hot Chips 2026 conference, held at Stanford University.1

The dual instruction set design leverages a shared decoding pipeline for most operations, though certain decoders remain separated to handle the distinct requirements of each ISA.1 A key innovation involves hardware-based byte-order conversion within the load-store unit, automatically managing the transition between z/Architecture's big-endian format and ARM's little-endian format.1 Unlike ARM's weak memory ordering model, all load and store operations on the z18 enforce total store order (TSO), ensuring strong ordering guarantees.1 The architectural expansion to support new floating-point formats, including BF16 and FP16, required relatively modest additional transistor allocation.1

Large structures including the translation lookaside buffer, caches, and physical register file are fully shared across both instruction sets.1 IBM designed this dual ISA approach to expand software ecosystem capabilities through ARM compatibility while enabling large-scale workload consolidation and AI applications.1 The Spyre chip variant integrates high-bandwidth memory (HBM), delivering single-chip memory bandwidth of 4 terabytes per second.1 Use cases now span from small fraud detection models to large language models and AI operations automation workflows.1 The company deliberately excluded POWER instruction set support to avoid competition with its existing IBM Power Systems product line.1