在为自研操作系统floss实现自旋锁时，开发者遭遇了一个硬件兼容性问题。1ldaxr（负载独占读取）指令在QEMU模拟器中运行正常，但在树莓派5硬件上触发数据异常。1具体表现为Data Abort exception，其异常代码（EC值）为37（0x25）。1
经过深入调查Arm文档和Cortex-A76 CPU的实现细节，问题根源得以确认：全局缓存控制寄存器SCTLR.C默认为禁用（值为0），且内存属性未配置为Write-Back模式。1根据Arm规范，原子操作需要内存属性为Inner Shareable、Inner Write-Back、Outer Write-Back Normal memory。1当这些条件不满足时，Cortex-A76 CPU无法通过全局独占监视器执行独占访问操作。1
Cortex-A76 CPU文档指出："页面仅当Inner和Outer内存属性都为Write-Back时才可缓存，其他情况下降级为Non-cacheable Normal memory"。1开发者通过将SCTLR.C位设置为1来启用缓存后，树莓派5上的异常消失。1此外，QEMU在v8.2.2升级到v11.1.50版本后加入了设备内存对齐检查，这解释了模拟器之前未能发现该问题的原因。1
A developer working on a custom operating system called floss for the AArch64 architecture encountered a critical issue while implementing spinlocks using the ldaxr (load-acquire exclusive register) instruction.1 The instruction functioned properly when tested in the QEMU emulator, but triggered a Data Abort exception on actual Raspberry Pi 5 hardware.1 Investigation of ARM documentation and CPU implementation details revealed the root cause: the global cache control register SCTLR.C was disabled by default, and memory attributes were not configured for Write-Back mode, preventing the Cortex-A76 CPU from executing exclusive access operations through the global exclusive monitor.1
ARM's atomic operation specifications require memory to be configured with Inner Shareable, Inner Write-Back, and Outer Write-Back Normal memory attributes for exclusive accesses to function correctly.1 According to the Cortex-A76 CPU documentation, pages can only be cached when both Inner and Outer memory attributes are set to Write-Back; otherwise they degrade to Non-cacheable Normal memory.1 The Data Abort exception generated by the ldaxr instruction carried an EC (Exception Class) value of 37 (0x25).1 Once caching was enabled by setting SCTLR.C=1, the exception disappeared on the Raspberry Pi 5.1
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