研究人员Christopher Domas发布了《Assembly Hall of Shame》项目，通过极端汇编优化技术对x86处理器单条指令的性能表现进行了系统测试 [1]。该研究揭示了CPU架构在指令执行延迟方面的性能边界和设计约束 [1]。
项目涵盖了27个指令样本，在Intel和AMD处理器上进行了测试 [1]。研究发现，性能表现跨度极大：最低延迟指令为nop，在Intel Core i7-8559U上仅需1周期 [1]；而最高延迟指令为fxrstor64，在AMD Ryzen 7 5800H上达到198,002,498,236周期，耗时62秒 [1]。
为了获得这些极端性能数据，研究采用了多种技术手段，包括利用PCIe fabric高延迟MMIO区域、饱和总线以及多核并行读取等方法 [1]。
Christopher Domas has released "Assembly Hall of Shame," a research project that investigates the extreme performance boundaries of individual x86 processor instructions through advanced assembly optimization techniques [1]. The study tested a diverse range of instructions across Intel and AMD processors, measuring their execution latency from best to worst case [1].
The research revealed dramatic performance variations across different instructions [1]. The fastest instruction measured was nop, executing in just 1 cycle or 0 nanoseconds on an Intel Core i7-8559U [1]. In stark contrast, the fxrstor64 instruction demonstrated the highest latency at 198,002,498,236 cycles, consuming 62 seconds on an AMD Ryzen 7 5800H [1]. The project encompassed 27 instruction samples in total [1].
To achieve these extreme measurements, Domas employed specialized techniques including leveraging PCIe fabric high-latency MMIO regions, bus saturation, and multi-core parallel reads [1]. This methodical approach exposed the underlying architectural constraints and design boundaries embedded within modern CPUs, providing insights into how processor design decisions affect instruction-level performance [1].