1995年，硅图公司(SGI)的John Mashey在Usenet comp.arch讨论组发布了关于128位处理器发展前景的技术分析[1]。Mashey基于当时的芯片设计趋势和内存容量增长规律进行了预测，认为从64位向128位处理器的过渡将是一个跨越数十年的长周期。
根据Mashey的分析，DRAM容量每3年增长4倍，相当于每3年增长2比特的物理地址空间[1]。基于虚拟内存压力的估计，128位处理器的大规模应用可能在2020年左右出现[1]。他同时指出，从1995年至2043年的约48年时间内，整个转变过程将逐步完成[1]。Mashey进一步推断，64位到128位的过渡周期应为32位到64位过渡周期的2倍[1]。
当时业界已经出现了36位和40位物理地址的芯片设计[1]。Mashey指出，实现128位处理器还需要克服包括1024位宽总线和长线延迟等重大物理设计挑战[1]。他的分析遵循指数级而非线性的时间规律，强调芯片架构演进遵循指数级发展规律[1]。
In a technical discussion posted to Usenet in September 1995, John Mashey of Silicon Graphics offered a comprehensive analysis of the timeline for the transition from 64-bit to 128-bit processors.[1] Mashey grounded his projections in observable hardware trends, particularly the exponential growth of DRAM capacity, which increases fourfold every three years or adds two bits to physical address width over the same interval.[1] Based on these metrics, he predicted that widespread adoption of 128-bit processors would emerge between 2020 and 2043, with alternative estimates placing the inflection point around 2020 when virtual memory pressure alone would drive the transition.[1]
Mashey's analysis emphasized that the shift would follow exponential rather than linear timing patterns, noting that the transition period from 64-bit to 128-bit architectures should take approximately twice as long as the prior shift from 32-bit to 64-bit systems.[1] At the time of writing, he observed that processors with 36-bit and 40-bit physical addresses had already begun to appear in the market.[1] Beyond the theoretical timeline, Mashey identified significant physical design challenges that would need to be overcome, including the necessity of 1024-bit-wide buses and the engineering complications posed by signal propagation delays across such wide interconnects.[1]